0003370: On i.MX6UL/ULL, DVS is on NAND_DQS which is configured as output high by Boot ROM

ID	Project	Category	View Status	Date Submitted	Last Update

0003370	NBootiMX6	NBoot	public	2018-02-23 16:46	2018-03-09 15:33

Reporter	Keller	Assigned To
Priority	normal	Severity	minor	Reproducibility	always
Status	resolved	Resolution	fixed
Product Version	V35
Target Version	V36	Fixed in Version	V36

Summary	0003370: On i.MX6UL/ULL, DVS is on NAND_DQS which is configured as output high by Boot ROM
Description	When booting from NAND, the Boot ROM loader configures NAND_DQS actually as NAND_DQS, i.e. as an output which is high. But we use this pad as DVS signal, which switches the core voltage level. 0: Regular voltage (1.36 to 1.42V), 1: reduced voltage (1.2V). Having this pin set high means we are booting with a reduced voltage of 1.2V which is OK for VDD_ARM at 400 MHz, but too low for VDD_SOC if the LDO is enabled. Then it should be at least 1.15V + 0.125V = 1.275V. Using this pad for DVS is not a good choice. It looks like we can not avoid the switching to high in Boot ROM. But we should switch it back to low as soon as possible to reduce the risk of boot failures due to the low voltage. Therefore we need this in NBoot.
Steps To Reproduce	Switch on board when booting from NAND, stop in NBoot, measure DVS signal -> high. Set Bootsel jumper, switch on board, download NBoot via MFG-tool, measure DVS signal -> low. So we can be sure that 1. NBoot does not set the signal to high and 2. Boot ROM only sets to high if booted from NAND.