0002668: Bad SPI timing on PicoCOMA5

ID	Project	Category	View Status	Date Submitted	Last Update

0002668	fsvybrid_Linux	SPI	public	2015-07-23 09:20	2017-02-13 11:30

Reporter	Keller	Assigned To
Priority	normal	Severity	minor	Reproducibility	have not tried
Status	resolved	Resolution	fixed
Product Version	fsvybrid-V2.1
Target Version	fsvybrid-V2.2	Fixed in Version	fsvybrid-V2.2

Summary	0002668: Bad SPI timing on PicoCOMA5
Description	Customer report: I tried to access external hardware over the SPI bus. Using /dev/spidev0.0 Running a lightly modified spi_test.c let some strange timing diagram appear on the logic analizer. 8 bits/word sending 3 bytes give not 382 baud: I expected the clock would be: CS0 10000000000000000000000001 byte: 111111112222222233333333 clock 010101010101010101010101 The LA shows: CS0 1000000000000000000001111 byte: 111111122222223333333xxx clock 101010110101011010101xxx I use gpio 41 as CS0 which is assigned in the structure spi_ioc_transfer.pad Trying to change clock phase or polarity cause an error message. Change the bits/word works but it unusable, we need 8/word The timing between lowering CS0 and rising clock is very small - few ns The clock low phase between two bytes is very small - fw ns The connected chip (CMX865A) is not responding.

Forum Link	http://forum.fs-net.de/index.php/Thread/3856-SPI-timing/