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| Reporter | Keller | Assigned To | | |
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| Priority | normal | Severity | minor | Reproducibility | always |
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| Status | resolved | Resolution | fixed | |
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| Product Version | fsvybrid-V1.1 | |
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| Target Version | fsvybrid-V1.2 | Fixed in Version | fsvybrid-V1.2 | |
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| Summary | 0002169: Fix filter settings for digital inputs |
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| Description | Signal changes on digital inputs (inc. interrupts) are onyl detected after a rather long period of time |
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| Steps To Reproduce | See SDA/SCL lines on audio I2C to SGTL5000 |
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| Additional Information | The filter for inputs are configured to use the maximum number of clocks (32) and in addition the slow clock (32kHz) is used instead of the fast clock (Bus clock). This is completely wrong and results in a minimum time to recognize signal changes of 1ms!!! Switch to fast clock and use smaller filter length. |
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