0002095: Improve display clock rate setting for Vybrid DCU

ID	Project	Category	View Status	Date Submitted	Last Update

0002095	fsvybrid_Linux	Display	public	2014-02-04 09:47	2014-04-07 15:15

Reporter	Keller	Assigned To
Priority	normal	Severity	minor	Reproducibility	always
Status	resolved	Resolution	fixed
Product Version	fsvybrid-V1.1
Target Version	fsvybrid-V1.2	Fixed in Version	fsvybrid-V1.2

Summary	0002095: Improve display clock rate setting for Vybrid DCU
Description	The current Vybrid implementation uses 113 MHz as base clock for the DCU. This only allows rather coarse settings of the pixel clock. For example a display that wants to hav 33 MHz can either have 28.25 MHz (divide by 4) or 37.7 MHz (divide by 3), which is both not very good. The hardware can provide much higher base clocks and we can even choose between two different clocks. This would allow a clock of 32.29 MHz or 34.28 MHz instead which would both be far better suited. Therefore improve the DCU driver to use the clock and setting that best fits the desired display clock rate.

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