View Issue Details
| ID | Project | Category | View Status | Date Submitted | Last Update |
|---|---|---|---|---|---|
| 0001721 | UBoot | Ethernet | public | 2013-04-09 12:41 | 2014-01-28 11:22 |
| Reporter | Assigned To | ||||
| Priority | normal | Severity | major | Reproducibility | always |
| Status | resolved | Resolution | fixed | ||
| Product Version | [Linux-Vybrid] V0.1 | ||||
| Target Version | [Linux-Vybrid] V0.1 | Fixed in Version | [Linux-Vybrid] V0.1 | ||
| Summary | 0001721: Use internal PLL to generate clock for ETH PHY is unstable | ||||
| Description | Use internal PLL to generate clock for ETH PHY is unstable: When removing Y3 and using RMII_CLKOUT we get timeouts and slow performance (fec_recv[232] err: 884) when using ETH in u-boot. Modifications in board/F+S/armstonea5/armstonea5.c: __raw_writel(0x001039c2, IOMUXC_PAD_000); /* RMII_CLKOUT */ puts("ETH1_1 SETTINGS.. "); temp = __raw_readl(0x4006B020); temp = temp | (2<<4); //[5:4] __raw_writel(temp, 0x4006B020); temp = __raw_readl(0x4006B014); temp = temp | (1<<24); //[24] __raw_writel(temp, 0x4006B014); temp = __raw_readl(0x400500E0); temp = 0x2001; //temp | (1<<0) | (1<<13); //[0,13] __raw_writel(temp, 0x400500E0); | ||||
| Steps To Reproduce | Vybrid U-Boot > tftp uImage_SPI Using FEC0 device TFTP from server 10.0.0.126; our IP address is 10.0.0.27 Filename 'uImage_SPI'. Load address: 0x80010000 Loading: #######fec_recv[232] err: 884 T ########################################################## ################################################################# ############################################################### done Bytes transferred = 2826788 (2b2224 hex) | ||||
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use CONFIG_FS_VYBRID_PLL_ETH to enable internal PLL for ETH clock. fixed with: commit 49e90af61e84cdad4d981b8354795ed1ab8a3c5c Author: Daniel Kuhne <kuhne@fs-net.de> Date: Fri Apr 19 15:58:01 2013 +0200 ETH: fix strapping options |
